1. Introduction

Running a behavioral simulation is different than actually implementing a script on a FPGA. There are two different methods to programming a FPGA with a Basys 3 board: the JTAG method and the QSPI method. All three of these operations are demonstrated to familiarize ourselves with the workflow and process of defining a digital circuit and implementing it with a FPGA and its memory.

2. Materials

• Basys 3 FPGA board
• Computer equipped with Vivado and a USB port.
• Micro-USB cable.

3. Procedure

Vivado was opened on a PC; a new RTL project was created, the appropriate chipset was selected for compatability with the Basys 3 board, a .xcf constraint file was attached to the project, and two .v files were created via the project set-up wizard. The first .v file was used to house the module script for an AND gate, and the second was used to house the testbench script.

A behavioral simulation was run to ensure the functionality of the AND gate. Once the simulation confirmed the logic, a second testbench file was created for use with the FPGA. This testbench file used variable names that were consistent with the constraint file uploaded to the project. This allows access to the pins on the Basys 3 board to upload the bitstream file to the FPGA to program the board.

Once the new testbench was ready, the code was synthesized, and some settings were changed. These changes can be seen in PDF 1 below.

PDF 1. This PDF contains screen-snips of the settings that were changed in Vivado to accomodate the Basys 3 board.

After the FPGA was programmed, the functionality was tested with the switches and LED on the Basys 3 board. The binary file was then uploaded to the memory of the FPGA by changing the jupmper from the JTAG pins to the QSPI pins and pressing the Program button on the PCB. This demonstrates both volatile, programming via PC with JTAG pins, and nonvolatile methods, with QSPI pins, for programming a FPGA.

PDF 2. This PDF contains screen-snips of the binary and bit-stream files being implemented in the FPGA programming process.

This process was repeated for both an OR gate and an XOR gate within the same project file in Vivado. This with minor changes. These changes included removing the steps for changing the settings in Vivado and removing/readding the Configuration Memory Device to ensure the proper binary file was uploaded to the FPGA.

4. Results

The AND gate, OR gate, and XOR gate simulations all confirmed the logic to be accurate to the respective logic gate as seen in PDF 3, Pages 1-3 respectivly.

PDF 3. This PDF contains the results of the behavior simulations ran in Vivado of the AND, OR, and XOR gates respectivly.

The Implemented Design resulted in a visual representation of the described digital circuit. These can be found in PDF 4.

PDF 4. This PDF shows the implemented design layout resulting from the AND, OR, and XOR gates respectivly.

The LED on the Basys 3 PCB also responded as expected when the switches were moved to provide all possible input combinations allotted with two bits. The volatile AND gate is demonstrated in Video 1a, and the non-volatile AND gate is demonstrated in Video 1b.

Video 1a. The volatile demonstration of the AND gate on the FPGA.                                                        Video 1b. The non-volatile demonstration of the AND gate.

The volatile OR gate is demonstrated in Video 2a, and the non-volatile OR gate is demonstrated in Video 2b.

Video 2a. The volatile demonstration of the OR gate on the FPGA.                                                          Video 2b. The non-volatile demonstration of the OR gate.

The XOR gate is demonstrated in Video 3 with the first portion being the volatile version and the second portion being the non-volatile version of the demonstration.

Video 3. The XOR gate demonstration. The first half is the volatile version, and the second half is the non-volatile version of the demonstration.

5. Discussion

At first the procedure was intimidating, but after performing the OR gate demonstration, it felt familiar. I did run into an issue with uploading the binary file to the FPGA, but with some help from Dr. Li I was able to resolve the problem. The constraint file also helps me a lot to understand exactly what I am accessing with Verilog through the scripts. I hope this continues to help me in the future when writing scripts to describe more advanced digital circuits.