3. Procedure
First, I converted the dimensions of the 50nm technology to C5 technology of the same resistivty. Then I created schematics for both 2 and 3 input NAND gates, a 2 input AND gate, and two different sized inverts (40/20 and 100/50 respectively) with these sizes. I made icons for each component and ran simulations to ensure everything still looked right; these can be found in PDF 1 below. Once this was done, I went ahead and converted all of the schematics given to us from LTSpice to the C5 sizes. Once this was done, I began designing the schematics in Electric VLSI.
First, I created the schematic for the Sample and Hold schematic. This schematic, the first schematic in PDF 1, contains the necessary components for a charge-pump and a low-pass filter to provide a steady V_GS to the pass gate of the sample-and-hold block. This is necessary to achieve an electric potential of 2VDD in the circuit to ensure the output is stable. Once this was complete, I created an icon view and simulated the circuit to ensure proper functionality. These results are showin with the schematic in PDF 1. The sample and hold circuit will sample the input signal, and once the clock signal has a rising edge, the sample will be tracked, and once the edge falls, the tracked value will be held until the next rising edge. This holding period is where the conversion takes place.
Next, I created the schematic for the D-Flip-flop from TI. This design has set and reset functionality. Once the schematic and icon was created and DRC clean, I simulated the circuit to ensure it worked properly. I also created a buffer out of two inverters. This is to help stabalize some signals in the SAR.
Once the D-Flip-Flop and buffer was done, I could move on to the 8-bit SAR. The SAR begins by initializing with 1 MSB. When connected to a comparator, it will intake the comparator's bit and place it in the bitstring by shifting out the original bits. This SAR requires 9 DFFs in each row, one for each bit in the bitstring and one to shift out the bits, totalling in 18 DFF blocks. This schematic and icon can be seen in PDF 1 below along with the simulation proving the functionality of the circuit.
I then laid out the schematic for the op-amp. This specific op-amp acts as a comparator. This is needed for the SAR mentioned in the paragaph above. These can also be found in PDF 1.
I then edited the 10-bit R-2R DAC from Lab 2 to create an 8-bit version. I edited the icon view as well, and I ran a simulation to check it. I simulated 00000001 to see if I got 1 LSB as the analog output. I calculated this with the equation Vin*(1/2^8), and I used 5V as the input for the simulation. The results can be seen in the PDF along with the others. We need two DACs for our simulation, but only one for functionality. The first one is for feeding into the comparator to carryout the conversion. The second one is just to verify our results from the door-register is being converted properly.
Once this was done, I needed to create the timing circuits. These were the 8-bit door register and the clock block. The clock block is just as important as the SAR to this SAR-ADC, as the components of the circuit rely on timing to be optimal/function properly. The clock block includes a 4-bit counter, to allow us to count for 12 counts, and three timing-logic circuits. These timing circuits counted to 10 for the clock-door to allow for the door register to open after the SAR shifts the output to it, counted to 11 for the Sample/Hold circuit to allow for the conversion to complete before tracking and holding another sample, and count to 12 to wait to reset the counter until the last clock update has finished. These extra counts should not affect the SAR as the output would already be sent before any more shifting could happen, as well as the same sample will be held in the positive terminal of the comparator.
The door register acts as a holding bay for the output from the SAR. This allows for more control of when the output is sent out to ensure that no bits are left behind in the conversion. This door register is made of D-Flip-flops that pass the input straight to Q, and is waiting for the clock to trigger it to release the value. I created icons for both components, and then I ran simulations for each as well. These can be found in PDF 1 below.
After all these schematics came out DRC clean, and the simulations showed satisfactory results, I laid out the schematic for the SAR-ADC. Once this was DRC clean, I simulated the circuit with a clock that had a 10% duty cycle. This was to ensure a decent resolution. These can be found in PDF 3.
Once the final simulation was complete, I exported the voltage data as a text file and created a python script to calculate the INLs and DNLs and plot the data. These can be seen in Figures 1,2, and 3 below.
I also wrote code to calculate all of the various values needed to fill out the specification table seen below in Figure 4. There are two values missing. I need to speak with Dr. Li for some clarification before I include those figures in the script.