ENGR-433 Spring 2023
Lab 3: Seven-Segment Display on a FPGA
Name: Cheyenne Tucson
Email: crtucson@fortlewis.edu

Seven-Segment Display on a FPGA

1. Introduction

It is important to know how to use the constraint file to access the various pins on a prototyping board equipped with a FPGA. Not only does this allow convenient testing of the digital circuit described to the FPGA, but it also allows access to the on-board oscillator crystal. This means that a clock can be implemented in a digital circuit described in Verilog! This lab will demonstrate this in various ways.

One way is through combinational logic concepts that describe and demonstrate the following digital circuits: an inverter (NOT Gate,) a 2-bit Full Adder, an 8-input AND gate, and a 4:1 Multiplexer (MUX.) Another way this is demonstrated is through using the LEDs and 7-segment displays on the Basys 3 board utilizing the switches and clock functionality provided through the constraint file; this gives us access to that lovely 100MHz crystal on the protoboard.


2. Materials


3. Procedure

Vivado was opened on a PC; a new RTL project was created, the appropriate chipset was selected for compatability with the Basys 3 board, a .xcf constraint file was attached to the project.

Verilog scripts for the following combinational logic blocks were written in gVim: an Inverter, a 2-bit Full Adder, an 8-input AND Gate, and a 4-1 MUX. Testbench scripts were then written in Verilog for both behavioral simulation and FPGA implementation for each combinational logic block. Once these scripts were completed, they were added to the project in Vivado and simulated/synthesized and the Basys 3 board was programmed with the bitstream files generated for each digital circuit described.

The next task was to create and implement a circuit that shows a running LED with a reset function. This was done by implementing a bit-shift with time delays in the circuit.

After the running LED was implemented successfully, the 7-segment display was implemented to show a running count from 0-9 on all four displays on the Basys 3 board. After the digits were successfully displayed, the script was modified to show the decimal value of a binary input. The binary input was achieved with switches.
Once this was done successfully, the script was changed to only display the decimal number on only one of the 7-segment displays.


4. Results

The behavioral simulation results can be found in PDF 1, Pages 1-4, of the Inverter, 2-bit Full Adder, the 8-input AND gate, and the 4:1 MUX respectivly. The recorded demonstrations of the combinational logic blocks can be seen below in Videos 1-4 in the same respective order to the pages in PDF 1.

PDF 1. This PDF contains the results of the behavior simulations ran in Vivado.

Video 1. The recorded demonstration of the NOT gate on the FPGA.                                                        Video 2. The recorded demonstration of the 2-bit Full Adder.

Video 3. The recorded demonstration of the 8-input AND gate on the FPGA.                                                        Video 4. The recorded demonstration of the 4:1 Multiplexer on the FPGA.

PDF 2. This PDF contains all of the Verilog scripts written and used to implement the various tasks involving the LEDs on the Basys 3 board.
The running LED circuit described in Verilog is shown in Video 5 below. The LED moves from right-to-left for four LED spaces. The reset switch returns the sequence to the rightmost LED on the board. The scripts written in Verilog that describe the circuit demonstrated in Video 5 can be found in PDF 2 above.
The results of the synthesized Verilog scripts for the counter using the 7-segment displays on the Basys 3 board are shown in Video 6: the first half of the video shows the count on all four displays, and the second half of the video shows the count on only one of the displays. The Verilog scripts written to describe the circuits demonstrated in Video 6 can also be found in PDF 2 above.
Video 5. The recorded demonstration of the running LED with a reset switch implemented on the FPGA.                                                         

Video 6. The recorded demonstration of the count displayed on both all four of the 7-segment displays on the Basys 3 board (first half of the video), and only one of the 7-segment displays on the board (second half of the video.


5. Discussion

Being able to implement the clock in a digital circuit is a crucial skill to know as an ASIC Engineer in the industry. It is noted that implementing these tasks on a FPGA was far more efficient than using a bulky decoder on a breadboard to display the count on a FPGA.