ENGR 338 Lab 9
Name: Zane Sauer
Email:
zmsauer@fortlewis.edu
Task 1:
![](MUX_DRC.JPG)
Figure 1: 2 to 1 MUX DRC clean
![](MUX_SIM_2to1.JPG)
Figure 2: 2 to 1 MUX sim
![](8MUXDRC.JPG)
Figure 3: DRC clean 8 bit MUX
![](8MUXSIM.JPG)
Figure 4: 8 bit MUX sim
![](2MUX_LAYOUT.JPG)
Figure 5: 2 to 1 mux layout DRC NCC ERC clean
![](8bitMUXLayout.JPG)
Figure 6: 8 bit MUX DRC NCC ERC clean
Task 2:
![](FA_schm.JPG)
Figure 7: Full Adder schm DRC clean
![](FASIM.JPG)
Figure 8: Full Adder Sim
![](FAlayoutsmn.JPG)
Figure 9: HS FA failed NCC
![](Casdfasda.JPG)
Figure 10: Simulation of HS FA
Conclusion:
Unforetunetly
I was not able to get the layout of the HS FA working under time
constraints I will continue to fiddle with it to see if I can get it
fixed.