ENGR 338 Lab 6
Name: Zane Sauer
Email:
zmsauer@fortlewis.edu
Introduction:
In this lab we created componets to build up to a full adder. These
components included a NAND gate, NOR gate and XOR gate. Once all
components were created I copied and pasted them into the main file of
the full adder.
Task 1:
Building NAND gate
![](img/NAND_DRC.JPG)
Figure 1: DRC clean of NAND gate
![](img/NAND_SIM.JPG)
Figure 2: Simulation results of NAND gate
![](img/NAND_layout_DRC.JPG)
Figure 3: DRC clean of NAND gate, note that this was modified later to work better with full adder
Task 2:
Schematic and layout of NOR gate
![](img/NOR_schm_DRC.JPG)
Figure 4: DRC clean NOR gate schematic
![](img/NOR_SIM.JPG)
Figure 5: NOR simulation results
![](img/NOR_layout_DRC.JPG)
Figure 6: DRC clean of NOR gate layout
Important to note that the wells of this were later change to pass ERC checks, changes can be seen in the full adder.
Task 3:
Design and layout of XOR gate
![](img/XOR_DRC.JPG)
Figure 7: DRC clean of XOR gate
![](img/XOR_SIM.JPG)
Figure 8: Simulation results for XOR gate, B pin is held high
![](img/XOR_SIM_2.JPG)
Figure 9: Simulation results for XOR gate, B pin is grounded
![](img/ECC_DRC_XOR.JPG)
Figure 10: DRC and ERC clean for XOR gate layout
Task 4:
Design and layout of Full Adder
![](img/FA_schm_DRC.JPG)
Figure 11: DRC clean for schematic of Full Adder
![](img/FA_SIM.JPG)
Figure 12: Simulation Results for Full Adder, note Cin was held low
![](img/FA_SIM_2.JPG)
Figure 13: Simulation Results for Full Adder, Cin is held high
![](img/FA_DRC_layout.JPG)
Figure 14: DRC clean for Full Adder
![](img/FA_ERC.JPG)
Figure 15: ERC clean for Full Adder
Conclusion:
This
was a challenging lab, and it took a lot of trail and error to get vias
and routing wire in the exact right spot to not cause errors. This was
a good and challenging lab and helped me learn alot about how to build
smaller modules to fit into a larger design more effectively.