ENGR336 Lab 2022 Fall
Lab 8: Design a MUX, and a High-Speed Full Adder
Name: Seth VanMatre
Email: sgvanmatre@fortlewis.edu

Design a MUX, and a High-Speed Full Adder

Introduction
The objective of this lab is to build a MUX and a High-Speed Full Adder.   

Materials and Methods
- Electric VLSI

Results
Task 1:  Build an 8-bit MUX.
MUX-Schematic
Figure 1: Simulated and Constructed 1-bit MUX.


MUX-Layout
Figure 2: Layout for 1-bit MUX.

MUX-8bit'
Figure 3: Simulated schematic of an 8-bit MUX.


MUX-8bit-Layout
Figure 4: 8-bit MUX layout.



Task 2: Build a 1-bit high-speed full adder.
HS-FA_Schematic
Figure 5: Schematic for high-speed full adder.

HS-FA_Sim
Figure 6: Simulated high-speed full adder.


HS-FA_Layout
Figure 7: Layout for the high-speed full adder.




Task 3: 8-bit high-speed full adder.
HS-FA_Bus_Sim
Figure 8: Simulated schematic for 8-bit full adder


HS-FA_8BIT_Layout
Figure 9: Layout for high-speed full adder.


Discussion
Constructing the High-Speed Full Adder was difficult becuase of the various connections and spacing between the vias. Although it was insightful on how this is constructed. The MUX was fun to build.