ENGR 433 Lab 2023 Spring
Lab 4: Combinational Logic Blocks
Name:
Seth VanMatre
Email: sgvanmatre@fortlewis.edu

Combinational Logic Blocks

Introduction

The objective of this lab is to simulate and implement a stoplight as well as a even parity generator and checker.

Materials and Methods
- Install Vivado 2018 version.
- Install gvim.

Results
Task 1: Drawl the truth table for all the states in one cycle of the traffic light change. Simulate the results in vivado then implement onto the Basys 3 board.
k-mapSTL.jpg
Figure 1: Stoplight truth table and K-map.

 STL_tbSim.png
Figure 1.1: Stoplight test bench.

STL_Sim.png
Figure 1.2: Stoplight simulation.



Task 2: Even parity generator and checker.

EvenPairityChecker&Gen_tb.png
Figure 2: Even parity generator and checker wire together.

EvenPairityChecker&Gen.png
Figure 2.1: Even parity generator and checker simulation.

EvenPairityChecker&Gen_tbBoard.png
Figure 2.2: Even parity generator and checker synthesis.





Discussion
I had extrem difficulty trying to get the stoplight algorithm to work. After I ran the simulation and verified that my logic is correct, I ran it on the board again and it worked. As for the even parity generator and checker, I had no difficulty in accoplishing this task.