ENGR 433 Homework 2023 Spring
Homework 4: Data Storage Units
Name: Seth VanMatre
Email: sgvanmatre@fortlewis.edu
Data Storage Units

Task 1: Repeat the simulation in Section 1 - 3.
SRLatch.png
Figure 1: SR Latch simulation.

SRFlipFlop.png
Figure 1.1: SR Flip Flop simulation.

DLatch.png
Fiugre 1.2: Level Triggered D Flip-Flop simulation.

DFlipFlop.png
Fiugre 1.3 Edge Triggered D Flip-Flop Simulation.


Task 2: Write the testbenches and run simulations for Sections 4 and 5.
JKFlipFlopCode.png
Figure 2: Edge Triggered JK Flip-Flop test bench.

JKFlipFlop.png
Figure 2.1: Edge Triggered JK Flip-Flop simulation.

TFlipFlopCode.png
Figure 2.2: T Flip-Flop Code test bench.

TFlipFlop.png
Figure 2.3: T Flip-Flop simulation.


Task 3: Repeat all the work in Section 8 and complete the task described in the end of Section 8.

8bitMem.png
Figure 3: ROM 8-bit binary number simulation.

hexMem.png
Figure 3.1: ROM hex number simulation.

8bithexMem.png
Figure 3.2: ROM 8-bit Hex simulation.

3bitMem.png
Figure 3.3: ROM 3-bit binary number simulation.

MyRom_TB.png
Figure 3.4: IP core myRom test bench .

MyRom_Sim.png
Figure 3.5: myRom simulation.