ENGR 433 Homework 2023 Spring
Homework 3: Combinational Logic Blocks
Name: Seth VanMatre
Email: sgvanmatre@fortlewis.edu
Combinational Logic Blocks

Task 1: Half Adder and Full Adder


FullandHalfAdderCode.png
Figure 1: Full Adder on the Left, Half Adder on the right.

HalfAdderSim.png
Figure 1.1: Half Adder Simulation.

FullAdderSim.png
Figure 1.2: Full Adder Simulation.

Task 2: Design teh testbench for the comparator and the simulation results.

ComparatorCode.png
Figure 2: One bit comparator module and test bench.

ComparatorSim.png
Figure 2.1: One bit comparator Simulation.



Task 3: Design the testbench for the 4-bit comparator and show the simulation results.

4BitCompCode.pngnBitCompSim.png
Figure 3: Four bit comparator code.

nBitCompSim.png
Figure 3.1: 4-Bit comparator code.

Task 4: 2-bit comparator on the Basys-3 board.

2bitCompCode.png
Figure 4: Two bit comparator code.


Task 5: Design the testbench for the decoder and verify the logic using simulation.

decoderCode.png
Figure 5: Decoder code with test bench.

decoderSim.png
Figure 5.1: Decoder Simulation.

Task 6: Encoder 8x3 Priority.

Q0Q1Q2.jpg
Figure 6: Finding Q1 and Q2.


Encoder8x3Code.png
Figure 6.1: Priority 8x3 Encoder.

Encoder8x3Sim.png
Figure 6.2: Priority 8x3 Encoder Simulation.

Task 7: Implemnting a 4-1 MUX to the Basys-3 board.

MUX4x1Code.png
Figure 7: 4-1 MUX code.



Task 8: Parity generator and checker.

EvenParityCheckerCode.png
Figure 8: Even parity checker code.

EvenParityCheckerSim.png
Figure 8.1: Even parity checker simulation.

EvenParityGenCode.png
Figure 8.2: Even parity generator code.

EvenParityGenSim.png
Figure 8.3: Even parity generator simulation.

EvenParityChecker&GenImpCode.png
Figure 8.4: Right even parity checker and left is the even parity generator.





Task 9: Implementation of the advanced home alarm and advanced car parking.