CE 433 Spring 2024
Quiz 4: Shift Register
Sahra Genc
sggenc@fortlewis.edu

QUIZ 4: Shift Register

Part 1. Type a serial in parallel out (SIPO) shift register design in gVim. Design a testbench for it's demonstration on a FPGA.
Part 2. Debug in Vivado, implment it on your Basys 3 board. Post your report to your website.


Figure 1. Implementation of the SIPO shift register


Video 1. Demonstration of SIPO displaying 1010 on the FPGA