CE 433 Spring 2024
Lab 2: Introduction to FPGA
Sahra Genc
sggenc@fortlewis.edu
LAB 2: Introduction to FPGA
Introduction
The focus of this lab was to build skills with Vivado and FPGA. The
tasks were including to adding design sources, writing testbenches,
running simulations and performing on-board logic verifications. We
coded and verified AND, OR and XOR digital gates and we learned about
volatile and nonvolatile FPGA programming.
Task 1: Go through all the
steps in this lab instruction, report your code, simulation results,
and the on-board verification results.
Figure 1. Module and testbench code for AND gate.
Figure 2. Vivado simulation of AND gate
Figure 3. Testbench code to verify logic on FPGA (same testbench code used for OR and XOR gates)
Video 1. Demonstration showing on-board verification of AND gate with nonvolatile method
Task 2: Use the same procedure to create XOR and OR gates. Run simulations to verify the logic.
Figure 4. Module and testbench code for OR gate
Figure 5. Vivado simulation for OR gate
Figure 6. Module and testbench code for XOR gate
Figure 7. Vivado simulation for XOR gate
Task 3: Use both the volatile and nonvolatile methods (QSPI) to program your FPGA. Show videos for the demonstrations.
Video 2. Demonstration showing on-board verification of OR gate with nonvolatile method
Video 3. Demonstration showing on-board verification of OR gate with volatile method
Video 4. Demonstration showing on-board verification of XOR gate with nonvolatile method
Video 5. Demonstration showing on-board verification of XOR gate with volatile method
Discussion
Completing this lab increased my comfort with Verilog, Vivado, and
FPGA. Getting experince with .bin and .bit files for volatile and
nonvolatile methods was interesting and valuable.
