Shift Register Quiz:

Noah Smith

The goal of this quiz was to write Verilog code to create a Serial in Parallel out shift register with a manually controlled clock.

Below is my code for this quiz. I used led’s [0:3] and Switch[0] as data and Switch[1] as my manual clock. I imported the debounce module from a previous quiz and used similar code for the SIPO register from HW5. It was then a simple matter of mapping the modules together with the mCLK wire in the Top module.

You can see in the demonstration video that every time I flip the clock switch the leds move one to the left and whatever the input from switch[0] is is the next bit that is passed into the right side.