Tasks 1 & 2
I started by writing the modules for all three gates in one .v file in gVIM and importing this file into vivado so that I had 3 design sources, 1 for each gate as seen below in Figure 1.
Figure 1. HDL code for and, or and xor gates.
These three modules were then all put into the same test bench. I did this by creating three seperate output variables but using the same two input variables to test the logic of all three gates at the same time. The testbench code can be seen below in Figure 2.
Figure 2. Test benches for all three simulations.
I then ran the simulation for all three gates to verify their logic as seen below in Figure 3.
Figure 3. Simulation results for all three gates.
I then uploaded the contraints file linking the physical pins on the Basys 3 to the HDL in vivado as well as changing the test bench to work with these new constraints.
Figure 4. New test bench for uploading to FPGA.
Task 3
The design was synthesized and I checked all the settings provided in the writeup. I luckily didn't have to change any settings since they were all set the way they should've been. The synthesized design can be seen below in Figure 5.
Figure 5. Synthesized design of all three gates wired to LED 0, 1, and 2.
The bitstream was then generated and pushed to the Basys3 board and can be seen in Figure 6.
Figure 6. Volatile Memory And, Or, XOR gate demo, LED 0 is the and output, 1 is the or output and 2 is the xor output.
I then used QSPI to upload the bit data to the memory of the board so that it was stored in non-volatile memory.
Figure 7. The nonvolatile programming method demo.