ENGR338 Lab 2022 Fall
Lab 1 Review of Superposition, Thevenin's Equivalent Circuit, and LTSpice
Name: Mason Brady
Email: mrbrady1@fortlewis.edu

Review of Superposition, Thevenin's Equivalent Circuit, and LTSpice

Introduction: This Homework was to learn how to use vivado by writing some code in HDL and then simulating it in Vivado
Materials GVIM, Vivado
Methods / Results:

I started by writing the code for examples 2.1 - 2.3 in gVIM which can be seen below in Figure 1.


Figure 1. HDL code for the same circuit in three different programming styles.

These code blocks all have the same functionality but are written in different styles. The first script uses structural modeling to model the gates and then extract the circuit behaviour, the second code block is dataflow modeling and is the most familiar to how I typically program in Python or C++. The behavioural modeling seems useful if you care about the intermediary logic but the code seems slightly more complex from this first trial.

The code was then simulated using the testbench code seen in Figure 2.

Figure 2. Test benches for all three simulations.

Since these scripts were almost identical the same test bench can be used by simply chaning the name of the UUT.

I ran all the simulations and to no surprise they were all the same so for concision I am only putting a single photo for the simulation results in Figure 3.


Figure 3. Simulation results for the scripts written in 2.1-2.3

To demonstrate blocking and non-blocking the following HDL code was written


Figure 4. Blocking and Non-Blocking HDL example script.

The testbench was then setup in vivado, almost the same as the prior examples but this time the clock is switched every 10ns.


Figure 5. Testbench for Blocking and Non-Blocking example.

The testbench wasa then run and yielded the following output.


Figure 6. Blocking Non-Blocking simulation.

You can see that the non-blocked value (Y[3]) didn't change until the second rising edge since on the first rising edge y[2] was still 0 when y[3] checked for the update.
The timing diagram was then drawn on paper as seen below in Figure 7.


Figure 7. Hand drawn timing diagram.

Finally, all of the modules were placed in on file in gVIM and then simulated in vivado. The gVIM windows can be seen below in Figure 8.


Figure 8. gVIM windows of merged module code.

*I spelt module wrong in all of these but I debugged it in Vivado since they have error detection.
Then the vivado simulation was run to make sure the logic still worked as seen in Figure 8.


Figure 9. Vivado simulation.

Discussion: This lab was pretty straight forward but it took some time to get everything setup and understanding the workflow between gVIM and Vivado.