CE 433 Embedded Devices

Midterm
Name: Lucien Verrone
Email: ljverrone@fortlewis.edu

Task 1:

    (a)    25.25 (10) = 11001.01 (2) => 0000 0000 0001 1001.0100 0000 0000 0000 (UQ16.16)

    (b)    25.25 (10) = 11001.01 (2) = 1.100101 * 2^4 = (-1)^(0) * 2^4 * 0.100101 = 0100 1110 0101 0000 = 4E50 (16)
             S = 0
             E = 15 + 4 = 19 = 10011
             F = 100101 0000

    (c)    -25.25 (10) = -11001.01 (2) = -1.100101 * 2^4 = (-1)^(1) * 2^4 * 0.100101 = 1100 1110 0101 0000 = CE50 (16)
             S = 1
             E = 15 + 4 = 19 = 10011
             F = 100101 0000

    (d)   Only the first z will have the new x and y values. This is because the second assignment is non-blocking and executes at once, resulting in the past values of x and y being written to z.

Task 2:

2ns clock code:

2ns clock simulation:

Task 3:

Six bit even/odd code:

Six bit even/odd simulation:

Task 4:

(a) Sequence detected of state diagram: 1101

    (b) State diagram, truth table, and logic expressions for 1010 sequence detector:

          Code for 1010 sequence detector:

1010 seuqence detector demonstration: