Quiz 4 - Serial-in parallel -out

CE 433 Embedded Devices

2024 Spring

Part 1:

Type a serial-in parallel-out shift register design in gVim. Design a testbench for it's demonstration on an FPGA. (No simulation needed)

Figure 1: The debounce and sipo modules from quiz 4 for implementing on an FPGA.

Part 2:

Debug it in Vivado, implement it on your Basys 2 board. post your report to your website today.

Figure 2: The debugged functions from part 1.

Figure 3: The vivado code for implementing on to the FPGA board.