Lab 7 Using Buses in ElectricVLSI
Jesse Duran
Spring 2021
ENGR 338
Introduction:
In this lab we are tasked with designing a ring oscillator and multi bit OR, NOR, NAND, and AND gates using buses
Task 1
![](Images/Ring_osc_schem_clean.png)
Figure1. Ring Oscillator schmematic
![](Images/Ring_osc_schem_sim.png)
Figure2. Ring Oscillator Simulation
![](Images/ring_osc_bus_schem.png)
Figure3. Ring oscillator bus layout
![](Images/ring_osc_bus_sim.png)
Figure 4. Ring oscillator Bus simulation.
![](Images/ring_osc_bus_lay_clean.png)
Figure 7. Ring Oscillator Bus layout clean
Task 2
![](Images/AND_schem_clean.png)
Figure 8. AND gate schematic clean
![](Images/AND_8bit_schem.png)
Figure 9. 8-bit AND schematic and icon. DRC clean
![](Images/AND_8bit_SIM_vdd.png)
Figure10. 8-bit AND simulation. input A =11111111, B = 10101010, AandB = 10101010
![](Images/AND_8bit_sim_gnd.png)
Figure 11. 8-bit and simulation. input A = 00000000, B = 10101010, output: AandB = 00000000
![](Images/AND_lay_clean.png)
Figure 12. AND layout DRC and NCC clean
![](Images/AND_8bit_lay_clean.png)
Figure13. 8-bit AND gate DRC and NCC clean
Task 3
![](Images/OR_schem_clean.png)
Figure14. OR schematic and icon DRC clean
![](Images/OR_sim.png)
Figure 15. OR simulation. Logic verified
![](Images/OR_lay_clean.png)
Figure 16. OR layout DRC and NCC clean
![](Images/OR_8bit_schem.png)
Figure 17. OR 8bit schematic and icon
![](Images/OR_8bit_sim_gnd.png)
Figure 18. OR 8bit simulation. A=00000000, B=10101010. AorB = 10101010
![](Images/OR_8bit_lay_clean.png)
Figure 19. OR 8bit layout DRC and NCC clean
Task 4
![](Images/NAND_8bit_schem.png)
Figure 20. NAND 8bit schematic DRC clean
![](Images/NAND_8bit_sim.png)
Figure 21. NAND 8bit simulation. A = 11111111, B= 10101010, AnandB = 01010101
![](Images/NAND_8bit_lay.png)
Figure 22. NAND 8bit layout DRC and NCC clean
Task 5
![](Images/NOR_8bit_schem.png)
Figure 23. NOR 8bit schematic and layout DRC clean
![](Images/NOR_8bit_sim.png)
Figure 24. NOR 8bit simulation A = 00000000, B= 10101010, AorB = 01010101
![](Images/NOR_8bit_lay.png)
Figure 25 . NOR 8bit layout DRC and NCC clean
Discussion
This taught us more about using single bit components in order to build
mulitbit ones. The concept of buses was introduced in the schematic
level. Buses are not availible in the layout view since the it serves
as a
simplification mechanism. In the layout view, everything is defined on
the bottom level, so we must define the connection ourselves. This is
similar to how we can make the 100:50 inverter simply in the schmeatic
then fully defined in the layout. We also learned about the array
function which helps in working fast. The ring oscillator was good for
explaining how the buses work and interesting to simulate. After the
layer lectures using different metals made more sense.