ENGR 338 -  Lab 4 2023 Fall

Name: Ian Van Horn
Email: imvanhorn1@gmail.com
Lab 4 MOSFETs and IV Curves

This lab introduces NMOS and PMOS MOSFET transistors. The schematics and layouts of both transistor styles were fabricated. Simulations were run in LTSpice

This lab requires the Eletric VLSI software

Lab Images:


Figure 1:Schematic of 4-Port NMOS with Spice Code


Figure 2. Schematic of 4-Port PMOS with Spice Code





Figure 3: Layout of 4-Port NMOS with Spice Code, Error Free


Figure 4: Layout of 4-Port PMOS with Spice Code, Error Free


Figure 5: Spice Simulation of NMOS Schematic


Figure 6: Spice Simulation of PMOS Schematic




Figure 7: Spice Simulation of NMOS Layout



Figure 8: Spice Simulation of NMOS Layout



Conclusion: This lab sucessfully taught how to layout and simulate NMOS and PMOS.