CE 433 Spring 2022
Homework 4
Name: David Lee
Email:
djlee1@fortlewis.edu
Data
Storage
Introduction:
In
this homework assignment we use create simulations to see the functions
of many different storage compents.
Materials and Methods:
vim, Vivado and a FPGA board
Results:
Task 1: Repeat the Simulation in Section 1-3
![](CE433Embedded/ClassWork/HW4/Task1.1SimCode.png)
Figure 1: Shows The code
for the SR Latch
![](CE433Embedded/ClassWork/HW4/Task1.1Sim.png)
Figure 2: Shows The simulation results of
the SR Latch
![](CE433Embedded/ClassWork/HW4/Task1.2SimCode.png)
Figure 3: Shows The Code for the SR
Flip Flop
![](CE433Embedded/ClassWork/HW4/Task1.2Sim.png)
Figure 4: Shows The Simulation of
the SR FF
![](CE433Embedded/ClassWork/HW4/Task1.2DSIMCode.png)
Figure
5: Shows the Code of the D_latch
![](CE433Embedded/ClassWork/HW4/Task1.2DSIM.png)
Figure
6: Shows the
code for the D_latch
![](CE433Embedded/ClassWork/HW4/Task1.3SIMCode.png)
Figure 7: Shows the Code of the
D_Flip FLop
![](CE433Embedded/ClassWork/HW4/Task1.2DSIM.png)
Figure 8: Shows the Simulation of
the D Flip Flop
Task 2: Write the Test
Bench and Run Simulations for Section 4 and Section 5
![](CE433Embedded/ClassWork/HW4/Task2.1SimCode.png)
Figure 9: Shows
the Code of the JK Flip Flop
![](CE433Embedded/ClassWork/HW4/Task2.1Sim.png)
Figure 10: Shows the
Simulation Results for the JK Flip Flop
![](CE433Embedded/ClassWork/HW4/Task2.2SimCode.png)
Figure 11: Shows
the code for the T Flip Flop
![](CE433Embedded/ClassWork/HW4/Task2.2Sim.png)
Figure 12: Shows the Simulation of
the T Flip Flop
Task 3: Repeat
All work in section 8
![](CE433Embedded/ClassWork/HW4/Task3-3bitCode.png)
Figure 13: Shows
the Code for Reading 3bit Binary
![](CE433Embedded/ClassWork/HW4/Task3-3bitSIM.png)
Figure 14: Shows the
Simulation for the reading the 3Bit Binary
![](CE433Embedded/ClassWork/HW4/Task3-8bitCode.png)
Figure 15: Shows
the Code of the 8bit HEX Memory
![](CE433Embedded/ClassWork/HW4/Task3-8bitSIM.png)
Figure 16: Shows the Simulation of
the 8Bit HEX
![](CE433Embedded/ClassWork/HW4/Task3BinaryCode.png)
Figure 17: Shows
the Code of the 8Bit Binary
![](CE433Embedded/ClassWork/HW4/Task3BinarySIM.png)
Figure 18: Shows the Simulation of
the 8bit Binary
![](CE433Embedded/ClassWork/HW4/Task3HEXCode.png)
Figure 19: Shows
the Code for the HEX Input
![](CE433Embedded/ClassWork/HW4/Task3HEXSIM.png)
Figure 20: Shows
the Simulation of the HEX
![](CE433Embedded/ClassWork/HW4/Task3ROMCode.png)
Figure 20: Shows
the Code used for the last part of task 3 Using the IP in Vivado using
ROM
![](CE433Embedded/ClassWork/HW4/Task3ROMSim.png)
Figure 21: Shows the
Simulation of the IP ROM.
Discussion:
This was assignment was straight
forward for the All the tasks execpt for the last part of task three. I
had a hard time getting the understanding of what the IP core was doing
within the program. Once this was explained to me I was able to get a
better Idea on what to do for the remainder of the task. Then once I
felt like I got it My simulation results looked incorrect because
everything was the same on the output. This was because the address' in
the file were all the same for most of the file. That is why I
incremented by 100 each iteration because of the limited simulation run
time in vivado. This allowed me to have an output that is able to
produce a varitey of results.