CE433 Embedded Devices
Homework 4 - Data Storage

Connor O'Keefe
Email: cwokeefe@fortlewis.edu

SR Latch/FLip Flop:

Fig 1. SR Latch verilog code.


Fig 2. SR Simulation



Fig 3. SR Flip Flop verilog code.


Fig 4. SR Flip Flop Simulation.

SR Latch/FLip Flop:

Fig 5. D Flip Flop verilog code.


Fig 6. D FLip Flop simulation.
Edge Triggered JK FLip Flop:


 Fig 7. JK Flip FLop verilog code.


Fig 8. JK FF simulation.
Toggle FLip Flop:


Fig 9. T FF Code.


Fig 10. T FF Simulation.
Read Only Memory:


Fig 10. 8-bit Bin3-bit ary Simulation


Fig 11. 4-bit Hex Simulation


Fig 12. 8-bit Hex Simulation


Fig 13. 3-bit Binary Simulation
Vivado IP Block:

Fig 14. Testbench for extracting data for coe file.
Note that integer, i, increments by 100 to show the data extraction easier for simulation.


Fig 15. Running simulation.