1. Introduction

Proficiency with tying together modules within a testbench is just as crucial as understanding 2's compliment and handling signed binary numbers while performing binary arithmetics This lab will combine these two skills to implement a 3-bit Full Adder/Subtractor onto a FPGA housed on a Basys3 board.

2. Materials

• Basys 3 FPGA board
• Computer equipped with Vivado, a raw text editor, and a USB port.
• Micro-USB cable.

3. Procedure

Vivado was opened on a PC; a new RTL project was created, the appropriate chipset was selected for compatability with the Basys 3 board, a .xcf constraint file was attached to the project.

A testbench was created in Verilog to use the Full Adder module from a previous assignment to define the circuit. A decoder script for the SSD on the Basys3 board was implemented as well. To begin, the result of the operation was shown via LEDs on the Basys3 with the input values coming from the switches on the board. A demonstraion of this can be seen below in Video 1. Once this was completed, the output was displayed on the SSD module with the sign shown as well. The demonstration of this can be found below in Video 2. The scripts used to implement the SSD version can be found in Figure 1 below.

4. Results

Figure 1. A screen-snip of the Verilog scripts used to describe the digital circuit of the signed 3-bit Full Adder.

Video 1. A recorded demonstration of the signed 3-bit Full Adder with the results displayed on LED only.

Video 2. A recorded demonstration of the signed 3-bit Full Adder with the results displayed on both LED and SSD.

5. Discussion

Being able to implement the SSD was a bit trickier than I remembered from the home alarm system lab. This goes to show that repeated use and practice is necessary for polishing the skill to be able to open a blank text file and start describing the digital circuit without any references.