Task 1

For the first task, the standard transmission protocol for UART data transfer was written as a Verilog module, along with a debouncer module for a button, to implement a counter (incrimented by a button push) that shows the count from 0-9 on a SSD. A video demonstration can be found below in Video 1.

Video 1. This is a recorded demonstration of the button counter displaying the count on the SSD.

Task 2

Once the counter was implemented with the SSD, another button-activated circuit was described with Verilog. This circuit sends the ASCII value of a character, starting with A, and incrimenting by 1 to display the characters in order on a serial monitor. A recorded demonstration of this can be found below in Video 2.

Video 2 This is a recorded demonstration showing the FPGA sending the ASCII value to the Serial Monitor.

Task 3

This circuit described in Verilog receives the ASCII value of a character typed into a Serial Monitor, and the value's binary representation is displayed on the LEDs on the Basys3 board. A recorded demonstration can be found in Video 3 below.

Video 3 This is a recorded demonstration showing the FPGA receiving the ASCII value from the Serial Monitor and displaying them on the LEDs of the Basys3 board.

Task 4

Once this was functioning properly, the circuit was altered to display the value on the SSD of the the Basys3 board along with the LEDs. A recorded demonstration can be found in Video 4 below.

Video 4 This is a recorded demonstration showing the FPGA receiving the ASCII value from the Serial Monitor and displaying them on both the LEDs of the Basys3 board and the SSD.