Task 1

For the first task, the standard VGA protocol for 640x480 resolution monitors operating at 60Hz was considered and used to display an image to a monitor through the FPGA. This was done in Vivado with both Verilog scripts for the top and VGA protocol modules and Vivado for the ROM and clock modules. These two ROM and clock modules were described through Vivado's IP catalog provided in the software. Examples of this can be found in Figures 1 and 2 below.

                                          

Figure 1. This is an image of the laptop running Vivado, the FPGA housing the image and data transfer protocols, and the monitor displaying the image from the FPGA.               Figure 2. This is a screen-snip of the code used to display the image to the monitor.

Task 2

Once an image file was successfully displayed on the monitor via the FPGA, a Verilog script to display a white screen was written and implemented with the FPGA. This demonstration can be found in Video 1 below, and the scripts can be found in Figure 3.

              

Video 1 This is a recorded demonstration showing that the FPGA is displaying the white screen to the monitor.                              Video 2. This is a recorded demonstration showing that the FPGA is cycling through the RGB colors on the monitor. This video also shows the scripts used to do this.

Figure 3. This is a screen-snip of the scripts used to perform the white screen, as seen in Video 1.

Once this was done, a script was written to cycle through frames of full color, in red (R), green (G), and blue (B) respectively. This can be seen in Video 2 above.