ENGR 433 - Tucson Homework 5

Task 1

For the first task, the logic equation for q_1[n+1] and y were found by looking at the State Table for the circuit. The gate-level schematic was created from the logic equation; this can be found in Figure 1 below.

Figure 1. This is a scan of the paper that hold the logic equation and gate-level circuit schematic for q_1[n+1] and y found from the State Table.

Task 2

After the logic equation and schematic was found and drawn, a sequence detector circuit was described in Verilog by looking at both the logic equation found in Task 1, and the Meeley State Diagram of the State Table from Task 1. Behavioral simulations were ran for each version of the sequence detector circuit. These can be found below in Figures 2a and 2b.

Figure 2a. This is a screen-snip of the simulation results and Verilog script used to describe a sequence detector based off the logic equation. Figure 2b. This is a screen-snip of the simulation results and Verilog script used to describe a sequence detector based off the Meeley State Diagram.

Task 3

Once the sequence detector was simulated in Task 2, a Meeley State Diagram was constructed to detect the sequence to 1011. The truth table of the state diagram was drawn out, and the logic equations were found from the truth table. Once the logic equations were found, a sequence detector circuit was described in Verilog to confirm the sequence is detected properly. These can be found in below in Figures 3a, 3b, and 3c.

Figure 3a. This is a screen-snip that contains the Meeley State Diagram, truth table, logic equation, and gate-level schematic for the sequence of the state diagram.

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Figure 3b. This is a screen-snip of the behavioral simulation results from Vivado of the sequence detector for the state diagram. f3c; Figure 3c. This is a screen-snip of the Verilog modules that to describe the sequence detector circuit for the state diagram.

Task 4

After the sequence detectors were completed and functioning as expected, four different types of shift registers were described in Verilog and simulated in Vivado. The types of shift registers described and simulated are as follows: Serial-In-Serial-Out (SISO), Serial-In-Parallel-Out (SIPO), Parallel-In-Parallel-Out (PIPO), and Parallel-In-Serial-Out (PISO). Screen-snips of the Verilog scripts behavioral simulations of each type of shift register can be seen below, respective to the list above, in Figures 4a-4x, 5a-5x, 6a-6x,and 7a-7x.

Figure 4a. A screen-snip of the simulation results of the 8-bit binary ROM. Figure 4b. A screen-snip of the Verilog script used to describe the 8-bit binary ROM.

Figure 5a. A screen-snip of the 16-bit hexadecimal ROM simulation and necessary Verilog scripts.

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Figure 5b. A screen-snip of the 8-bit hexadecimal ROM simulation and necessary Verilog scripts.

Figure 6a. A screen-snip of the 3-bit binary ROM simulation and necessary Verilog scripts.

Figure 7a. This is a screen-snip of the ROM that was generated in Vivado via an IP core. Figure 7b. This is a screen-snip of the testbench script written in Verilog used for the behavioral simulation.

Figure 7c. This is a screen-snip of the simulation results of the ROM reading the "dsImage.coe" file.

Task 5

A counter module was described and simulated with Vivado and Verilog. The screen-snips of the behavioral simulation and Verilog scripts can be found below in Figure 8.

Figure 8.

Task 6

A gate-level schematic was provided for us. From this schematic, the logic equation of the circuit was found. Once this was found and simplified to my liking (as allowable through Boolean algebra,) the digital circuit was described in Verilog and a behavioral simulation was ran in Vivado. The logic expression can be found below in Figure 9a, and the simulation and Verilog scripts can be found in Figure 9b and 9c.

Sequential Circuit