Being able to layout an 8-bit MUX with busses and a High-Speed Full Adder are critical skills to have if aspiring to work in the field of IC design. The high speed full adder is faster than the one we designed in lab 6 because of the space being saved.
First, I created the schematic for the 2:1 MUX and ran a simulation in LTSpice to confirm the logic. Next, I created a schematic for an 8-bit version of a 2:1 MUX. I also ran a simulation in LTSpice to confirm the Logic. These can be found in PDF 1 below.
I then laid out the physical design of the 1-bit MUX and ensured there were no errors with a DRC, NCC, and wells check. This can be found in PDF 1 also. Then I created the 8-bit version's layout, and then I ran DRC, NCC, and wells checks for this layout design as well. I'm proud to say that I recieved an error-free NCC report on the first go!
After this was done, I laid out the schematic for the high-speed full adder. I then ran a simulation to confirm the logic. This is also found in PDF 1.
Once that came back DRC error free, I began to lay out the physical design of the high-speed full adder. This can be found in PDF 1 also.
I ran out of time due to catching up from losing my library during lab 7's completion. Unfortunately, this meant that I only gave myself one week for this two-week lab. Set-backs in another class where I had to start completely over on an assignment also contributed to this. Hopefully, there will be no more lags in this class now. I did notice that having to rebuild my library helped me train my skills in layout design. This was proven to me when I laid out the 8-bit MUX fairly efficiently. The lost points towards my grade were traded for experience, and I think it is a trade I'm okay with.