CE433 Lab 2023 Spring
Lab 6: Basys 3 FPGA to Implement a VGA Driver
Name: Vann Montoya
Email: bvmontoya@fortlewis.edu

    Basys 3 FPGA to Implement a VGA Driver
Introduction
The purpose of this lab is to familiarize ourselves with the VGA port on the FPGA.

Materials and Methods
FPGA
Vivado
gVim
Monitor
VGA cable

Results
Task 1. Draw a green line on a white background on the monitor. (25 points)   

Figure 1: Here is the FPGA programmed to display a vertical green line on a white background.


Task 2. Draw an additional red bar on the monitor (25 points)

Figure 2: Here is the FPGA programmed to display an additional red bar on the right side.


Task 3. Move the red bar to the right (horizontally) by 1 pixel for every 0.5 second. (25 points)

Video 1: The FPGA programmed to move the red bar horizontally.


Task 4. Bounce it back and forth between the green line and the X location of 600. The speed is 0.01s/pixel. (25 points)

Video 2: The FPGA programmed to make the red bar bounce off the green line.