CE433 Lab 2023 Spring
Lab 5: A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers
Name: Vann Montoya
Email: bvmontoya@fortlewis.edu

    A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers

    Introduction
     The purpose of this assignment is to create a three bit adder and subtractor in 2's complement.

    Materials and Methods
    FPGA
     Vivado
     gVim

    Results
     Task 1: (40 points) Use switches as the 3-bit inputs, use 'leds' to show the binary results.
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     Task 2: (60 points) Use switches as the 3-bit inputs, use seven-segment displays to show the decimal result, make sure have the 'minus' sign in front of the decimal number if the result is negative.
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     Video 2: 3-Bit adder/subtractor using 7 segment display.