Lab4

CE 433 Lab 2023 Spring
Lab 4: Combinational Logic Blocks
Name: Vann Montoya
Email: bvmontoya@fortlewis.edu

    Combinational Logic Blocks

    Introduction:
The purpose of this lab is to implement combinational logic blocks.

    Materials and Methods:
gVim
Vivado
Basys 3 FGPA board

    Results :
Task 1: Draw the truth table for all the states in one cycle of the traffic light change. Simplify the logic equations for each light using the K map. Design the Verilog model and the testbench, show the simulation results in Vivado. Use 6 leds on your Basys 3 board to implement the design. Show the demo video for credits. (50 points)

    Traffic Light:

Here the truth table for the traffic light logic:

Inputs			Light 1			Light 2
X₀	X₁	X₂	G₁	Y₁	R₁	G₂	Y₂	R₂
0	0	0	0	0	1	1	0	0
0	0	1	0	0	1	0	1	0
0	1	0	0	0	1	0	0	1
0	1	1	1	0	0	0	0	1
1	0	0	0	1	0	0	0	1
1	0	1	0	0	1	0	0	1
1	1	0	0	0	1	1	0	0
1	1	1	0	0	1	0	1	0

Table 1: Truth table for the traffic light system.

Creating K-Maps for each of the lights, we get:

Figure 1: K-Maps used to simplify logic from the truth table.

From the K-Maps we get the following logic:
    G₁ = X₀X₁X₂
    Y₁ = X₀X₁X₂
    R₁ = X₀X₁ + X₀X₂ + X₁X₂

    G₂ = X₀X₁X₂ + X₀X₁X₂
    Y₂ = X₀X₁X₂ + X₀X₁X₂
    R₂ = X₀X₁ + X₀X₁

Here's the code for the traffic light module:

Figure 2: Traffic Light module.

The way the code has been set up, traffic light 1 is simulated with leds 5-3 starting with green, traffic light 2 is represented with leds 2-0 starting with green and the inputs are using switches 2-0 as shown below:

Figure 3: FPGA labeled with inputs and outputs.

Here is a YouTube Link demonstrating the FPGA programmed with the logic.

Even Bit Parity Checker and Generator:

An even bit parity checker is meant to check for errors due to noise from the parity generator.
A parity generator is to display whether the toggled bits are even, it will display when the bits are uneven.

Here's the code for the even bit parity generator and checker modules:

Figure 4: Code for the Even Bit Parity Generator and Checker.

Here's a diagram for the FPGA programming:

Figure 5: Diagram of the FPGA inputs and outputs.

Switches 0 through 3 represent the bits being passed through. So anytime an odd number of bits have been toggled, led 1 would light to make an even set of bits. Led 0 will light if and odd number of bits are detected after the even bit parity generator has corrected to an even number of bits indicating an error with the generator.

However, since there is very little to no chance for error in such a simplified system, led 0 should never light up indicating no error with the generator.

Here is a Youtube link demonstrating the FPGA programmed and its logic.