CE
433 2023 fall
HW3
Name: Anders Burdick-Levang Email:
aaburdicklevang@fortlewis.edu
HW #3 1.
Repeat the simulation of Half Adder and Full Adder in Section 1. Show
the code, code explanations, and simulation results in your report.
2.
Design the testbench for the comparator in Section 2. Show the code,
code explanations, and simulation results in your report.
3.
Design the testbench for the 4-bit comparator in Section 3. Show the
code, code explanations, and simulation results in your report.
4.
Implement a 2-bit comparator on the Basys 3 board. Use sw as inputs and
led as outputs. Show the code, code explanations, and an embedded
Youtube video demonstration in your report.
5.
In Section 4, design the testbench for the decoder and verify the logic
in simulation (use the Dataflow modeling method). Show the code, code
explanations, and simulation results in your report.
6.
In Section 5, for the 8x3 priority encoder, find Q2 and Q1, build the
module and verify the logic using simulations. Show the code, code
explanations, and simulation results in your report.
7.
Derive the logic expression of a 4-1 multiplexer. Show the process on a
paper, insert it as an image into your report.
8.
In Section 6, implement a 4-1 multiplexer on your Basys 3 board. Show
the code, code explanations, and an embedded Youtube video
demonstration in your report.
9.
Design/verify an even parity generator and checker in simulation
respectively. Implement an even parity checker on your Basys 3 board -
use sw as inputs, use leds as output indicators. Show the code, code
explanations, and an embedded Youtube video demonstration in your
report.
10.
Implement the design in Section 8 and Section 9 on your Basys 3 board.
Show embedded Youtube video demonstration on your report. Show the
code, code explanations, and an embedded Youtube video demonstration in
your report.
