CE 338: Digital VLSI Design (Laboratory), Spring 2025
Labs:
1/16,  Lab 1 Design an R-2R DAC.
Lab lecture video
1/23, Lab 2 Layout the R-2R DAC.
Lab lecture video
1/30, Lab 3 MOSFETs and IV Curves.
Lab lecture video
2/6, Lab 4 The Inverter.
Lab lecture video
2/13, Lab 5 Build a NAND, NOR, XOR, and Full Adder.
Lab lecture video
2/20,  Lab 6 Using Buses in ElectricVLSI.
Lab lecture video
2/27, Lab 7 Design a MUX, and a High-Speed Full Adder.
Lab lecture video
3/6, Lab 8 Design an 8-Bit ALU. (2-week lab)
3/13, Keep working on Lab 8.
3/27, Lab 9 Cadence Virtuoso 1 - 3
4/3, Lab 10 Cadence Virtuoso 4 - 7 (Tutorial 7 is on tsmc180, request Dropbox access if you have signed the NDA).
4/10, Lab 11 Cadence Virtuoso using the tsmc180nm PDK.
4/17, Lab 12 Cadence RTL to GDS flow (I'll be traveling to North Dakota State Univeristy for a DOT grant meeting)
Complete the following two tutorials (in Dropbox) for Lab12:
Tutorial_Xcelium
Tutorial_3_Genus_Innovus_Basics








Links:

Download LTSpice here

**LtSpice is available in BH 570 and SFH 2771: Open My PC - C Drive - Program Files - LTC, you can find LTSpice there, right click on the icon, and create a shortcut onto your desktop.

The C5_models.txt file   

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