ENGR337 Lab 2020 Spring
Lab 7:Tutorial 2
Name: Ryan Ford
Email: rwford@fortlewis.edu
Introduction:
The purpose of this lab was to familiarize students with ElectricVLSI
by having them run through a series of excercises.
Materials and Methods:
The materials used in this lab included LTspice and ElectricVLSI.
Follow the instructions specified in Lab 7, tutorial 2 on yilectronics.com.
Results:
Figure 1 shows the PMOS layout. Figure 1a shows the LTspice results.
Figure 1: PMOS Layout
Figure 1a: LTspice results for PMOS
Figure 2 shows the NMOS layout, and figure 2a shows the LTspice simulation .
Figure 2: NMOS Layout
Figure 2a: NMOS LTspice results
Figure 3 shows the PMOS schematic, and figure 3a shows the LTspice simulation.
Figure 3: PMOS schematic
Figure 3a: PMOS LTspice simulation
Figure 4 shows , and figure 4a shows .
Figure 4: NMOS schematic
Figure 4a: NMOS LTspice simulation
Discussion:
All
of the results matched the expected resuts
shown in Lab 7, tutorial 2 on ylectronics.com. Note that the
LTspice simulations match for NMOS and PMOS layouts and simulations
respectively.
