ENGR337 Lab 2020 Spring
Lab 6 Layout an N-Well Resistor and Voltage Divider in ElectricVLSI
Name: Jesse Duran
Email: Jiduran@fortlewis.edu

1. Layout an N-Well Resistor and Voltage Divider in ElectricVLSI

2. Introduction
This lab students were tasked with following through and completing Tutorial 1 of the ElectricVLSI series. A voltage divider was layed out composed of two n-well resistors and the results were simulated using LTSpice.

3. Materials and Methods

Materials

LTSpice

ElectricVLSI

The tutorial followed can be found at Yilectronics.com

4. Results


Figure 1. Schematic layout of voltage divider


Figure 2. LTSpice sim from schematic . Vout is 50% of Vin


Figure 3. CMOS layer(top view) 10KΩ resistor made from n-well, layed out as a voltage divider


Figure 4. LTSpice sim of CMOS layout. Vout is 50% of vin

5. Discussion
This lab tied together the usefulness of our spice code knowlege as well as introduced a powerful and desirable skill of CMOS layout. Being able to link LTSpice and ElectricVLSI proved to streamline the simulation process.