1. Think about how many
states the two-way traffic lights may have for each cycle.
The green light on one side truns yellow and then turns red before
the other light changes to green from red. The last state is crossed out because it repeats the first state.
Draw the truth table for
all the states in one cycle of the traffic light. Simplify
the logic equations for each light using a K map. Design the Verilog
model and the testbench, show the simulation results in Vivado (simulations are optional but they offer an extra 10 bonus points). Use 6
LEDs on your Basys 3 board to implement the design. Show the demo video
for credits. (50 points)
This is a practice on combinational logic, truth table, K-map, and logic simplification. The regular mode:
G1 = Y1 = R1 = G2 = Y2 = R2 =
The rush hour mode: The highlighted one is an added entry to keep the same state when the input is incremented by one.
G1 = Y1 = R1 = G2 = Y2 = R2 = 2. While the first problem cycles through all states with the same
durations, during rush hours, the busy road has a longer duration for
the green light than the red light. Use a switch to trigger the
rush hour mode which keeps one of the green lights ON for double the
duration compared to the other road. Show the code, code explanation, and demo video in your report. ( 50 points)
For
Task 2, the Case statement in Verilog will be very helpful. The
following example shows a submodule that takes in the input from port
'rush', firstly it was assigned to a reg data type 'rusninput', then
'rushinput' was used for the Case statement. This code simply turns
light1[5:3] on/off based on the sw[1]'s state. We can add the required
logic to this template to compelte Task 2.
