Lab 3 The Seven Segment Display Module

First, make sure you have the '##7 segment display' section in your constraint file uncommented.

The circuit diagram for the 7-segment display and the FPGA can be found in the datasheet of Basys3.

 

A snapshot of the constraint file. Compare with the schematic above, could you tell if seg[0] controls the LED at "A" or "G"?
Do you need W4 to be low or high to enable the MSB of the SSD? Do you need W7 to be low or high to turn on CA?

In the schematic above, next to "W7", it shows "CA" so it indicates it is for the "A" LED.





Tasks:
1. Show the same static numbers on all four display modules. The final result should show numbers 0-9. (20 points)
2. Use sw[3:0] to provide binary inputs and the 4 7-segment display show the corresponding decimal numbers. (20 points)



Examples:



3. Modify the code, disable any 3 of the 7-segment displays and only show the number on one of the displays. (20 points)
4. Show "FLC" on three of the display units. (20 points)
5. Roll "FLC" to the left for every half second. After "F" shifted out to the left, it should appear on the right hand side. Show your code, explanation, and demo video. (20 points)

Examples: