module andGate(a,b,y); input a,b; output y; assign y=a&b; endmodule `timescale 1ns/1ps module andGate_tb; reg in1,in2; wire out; andGate uut(.a(in1),.b(in2),.y(out)); initial begin #5; in1=1'b0;in2=1'b0; #5; in1=1'b0;in2=1'b1; #5; in1=1'b1;in2=1'b0; #5; in1=1'b1;in2=1'b1; end endmodule