Combinational Blocks

Combinational Logic Blocks

1. Adder

One-bit half adder:

Vivado simulation (including testbench)

One-bit full adder

Vivado simulation:

In the full adder testbench, when there are many simulation entries, you can use a for loop to simplify it.

2. Comparators

We may need to compare the magnitude of two binary numbers to obtain their status. Here, the first number may be greater than the second. The two numbers may be equal. Or, the first number may be less than the second. To achieve this goal, we will need a comparator. We can explain the comparison operation on two binary variables x and y (each being one bit) using the truth table presented in the following truth table. Here, g, e, and l stand for greater, equal, and less, respectively.

In Verilog:

3. Conditional statement in Verilog

A 4-bit comparator

An N-bit comparator can be constructed by the 'if' keyword. Here, two vectors each with four-bits (x and y) are compared and the result is written to another vector comp. If the first vector is greater than the second one, then comp[2]=1. If the second vector is greater than the first one, then comp[0]=1. Finally, if the two vectors are equal, then comp[1]=1.

Another example of the IF Statement (not a comparator):

If I remove the 'begin/end' statement in the IF statement and keep 'B<=B+1' below the 'A<=4'h0' line, B will have an increment of 1 at each cycle.

This example tells you that the 'begin/end' block defines the boundary of the IF statement if you have multiple lines there.

4. Decoders

In Verilog,

The 'case' statement

5. Multiplexers

A four-to-one multiplexer

In Verilog

The 'case' version. (an 8-1 multiplexer).

6. Parity generators and checkers

While transferring or storing binary data, some bit values may change because of a physical effect or an unpredicted disturbance. To check whether such an undesired change has occurred or not, extra bits can be added to the data. This is called parity generation. The idea here is setting standard characteristics to data such that when a change occurs, it can be detected easily.

Even Parity Generator - The total number of 1's in input and the parity bit are even
Odd Parity Generator - The total number of 1's in input and the parity bit are odd

Even Parity Generator (make the total number of 1's even)
Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity bit P. The figure below shows the truth table of even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

Use a K Map to find the logic expression of the truth table:

The above expression can be implemented by using two XOR gates. The logic diagram of even parity generator with two XOR gates is shown below. The three bit message along with the parity generated by this circuit which is transmitted to the receiving end where parity checker circuit checks whether any error is present or not.

In Verilog:

Even Parity Checker

It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even parity checker or odd parity checker depending on the type of parity generated at the transmission end. When this circuit is used as even parity checker, the number of input bits must always be even.

Even Parity Checker Consider that three input message along with even parity bit is generated at the transmitting end. These 4 bits are applied as input to the parity checker circuit, which checks the possibility of error on the data. Since the data is transmitted with even parity, four bits received at circuit must have an even number of 1s. If any error occurs, the received message consists of odd number of 1s. The output of the parity checker is denoted by PEC (Parity Error Check). The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the 4-bit message has even number of 1s.

Odd Parity Generator (make the total number of 1's odd)

Truth table:

Logic expression:

Circuit:

Odd Parity Checker

Logic expression:

The circuit:

7. Improving the home alarm system

We can improve the home alarm system using a seven-segment display. When the system is active, the display will show character A. When it is closed, the display will show character O.

To do so, we should add a seven-segment display decoder module to the system. This module converts the provided hexadecimal number to the corresponding seven-segment display pattern.

In which sw[4] is just a switch to turn ON/OFF the alarm but not triggering it. sw[3:0] are the triggering signals.

Please refer to the last tutorial to implement the improved home alarm system on your Basys3 Board.

8. Improved car parking spot counting system

It is simply adding all the bits together. The maximum count is 9 so how many bits do you need for c[]?

You must reuse the decoder_7seg module for this example.

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Tasks
1. Design the testbench for the comparator in Section 2. Show the code, code explanations, and simulation results in your report. (10 points)
2. Design the testbench for the 4-bit comparator in Section 3. Show the code, code explanations, and simulation results in your report. (10 points)
3. Implement a 2-bit comparator on the Basys 3 board. Use sw as inputs and led as outputs. Show the code, code explanations, and a link to the video demonstration in your report. (20 points)
4. In Section 4, design the testbench for the decoder and verify the logic in simulation. Show the code, code explanations, and simulation results in your report. (10 points)
5. Design/verify an even parity generator and checker in simulation respectively. Implement an even parity checker on your Basys 3 board - use sw as inputs, use leds as output indicators. Show the code, code explanations, and a link to the video demonstration in your report. (30 points)
6. Implement the design in Section 8 and Section 9 on your Basys 3 board. Show your code and link to the demo video in your report. (20 points)