F1 · MF-MSMF050

Resettable PTC: holds 500 mA, trips on a short, recovers when cooled.

Z1, Z2 · CG0603MLC-05E

Varistors clamp ESD on D− and D+.

L1 · BLM21 ferrite

Bonds the connector shield to GND through an HF impedance.

RN3 · 22 Ω

Series terminations on D± match the 16U2 driver to the ~90 Ω cable.

Auto-reset

DTR → C5 100 nF → RESET: a short pulse restarts the 2560 for upload.

RESET-EN

Solder jumper: cut it to stop resets when a terminal opens.

Serial link

M8TXD/M8RXD reach PE0/PE1 through 1 kΩ (RN6) — a header can override them safely.

ICSP1

6-pin header to reflash the 16U2 firmware.

Decoupling

4 VCC/GND pairs; C1, C16, C17 = 100 nF. Where they sit matters (Lecture 2).

AVCC LC filter

L3 10 µH + C19 100 nF → f₀ = 1/(2π√LC) ≈ 159 kHz.

Clock

Y3 CSTNE16M0 resonator with built-in load caps; R23 1 MΩ.

Reset

10 kΩ pull-up, D5 clamp, ICSP2 and RESET2 button.

Shield compatible

PWML/H, ADCL/H, COMMUNICATION and XIO follow Mega pin numbering.

Accelerometer

I²C (SDA/SCL) + 5 V, 10 kΩ pull-ups (RN5).

Ultrasonic

4-pin: 5 V, PG1, PG0, GND.

Watch for

Pins with two jobs — ADC0, PH5/PH6, the SPI pins.

Down-shift

U3 runs at 3.3 V; LVC inputs tolerate 5 V, so PB0–PB2 → card is safe.

Series 3.3 kΩ

R19–R22 limit current into the buffer inputs.

Up-shift

Card MISO → 4A → 4Y → PB3: a 3.3 V high into a 5 V AVR.

Teaser

Look at the four OE pins. Are they all OK? (Lecture 2)

Reference

Red LED D4 holds Q1’s base near 1.8 V.

Current sink

I ≈ (1.8 − 0.7) V / 2.2 Ω ≈ 0.5 A, nearly independent of the 5 V rail.

Base drive

(5 − 1.8) V / 300 Ω ≈ 11 mA from PL4 via JP8.

Receiver

U1 38 kHz demodulator on 3.3 V → PL5.

Top · signals + parts

FR-4 core 1.6 mm

Bottom · signals / GND

L1 · signals + parts

prepreg

L2 · solid GND

core

L3 · power pours

prepreg

L4 · signals

Through-hole via

Drilled through all layers. Cheapest; the only kind on Skyboard.

Blind via

Outer layer to an inner layer only. Extra process steps.

Buried via

Between inner layers; invisible from outside.

Microvia (HDI)

Laser-drilled, one layer deep. Phones and fine-pitch BGAs.

Place before you route

Placement decides most of the routing quality.

Critical nets first

Power, clocks, USB and analog; wide buses last.

One direction per layer

On 2 layers: top mostly horizontal, bottom vertical, via at each turn.

Fan out big ICs

Short stubs and vias outward from QFP pins before routing buses.

Net classes + DRC

Width and clearance per class; let the DRC police them.

Short and direct

Few vias, no stubs or loops; enter pads straight, not at a slant.

Red / blue

Top / bottom copper. Two layers, no internal planes.

Green rings

Through-hole pads and vias.

Grey

Silkscreen, outlines, part values.

Corners

Four 2.8 mm mounting holes, Arduino-style header rows.

Edges first

Connectors (USB, SD, headers) are placed by mechanics.

MCU centre

The 2560 sits where its 86 I/O fan out to all headers.

Analog corner

Mic and PWM DAC grouped bottom-left.

Question

Does each zone have a quiet return path? (Lecture 2)

Q1 if PL4 stays high

V꜀ₑ ≈ 5 − 1.5 − 1.1 = 2.4 V → ≈1.2 W vs ~0.35 W for SOT-23.

R18

I²R = 0.5² × 2.2 = 0.55 W vs 0.125–0.25 W for a chip resistor.

Budget

0.5 A ≈ the entire USB budget; pulses droop the shared 5 V.

Fix

Cap duty in firmware + higher-power R18 and SOT-89/MOSFET, or ~100–200 mA. Add a 100–470 µF reservoir.

Observation

4OE is tied to GND, so 4Y drives PB3 (MISO) all the time.

Risk

During ISP the 2560 drives MISO too → contention. No other SPI device can share the bus.

Fix

Drive 4OE from SS_CARD so it only talks when the card is selected.

Also

Add a 10 kΩ pull-up on SS so the card stays deselected during reset.

Observation

INB+ and INB− are unconnected; OUTB is open.

Risk

Floating inputs can oscillate, add supply current and inject noise.

Fix

Wire B as a follower: OUTB → INB−, INB+ to a fixed voltage (GND or mid-rail).

Verify

L13 is driven from PB1 (SCK), not PB7. Intentional SPI activity LED?

ESD return

Z1/Z2 clamp to the shield node, which reaches GND only via L1. A ferrite slows the very edge you want to shunt.

Fix

TVS array (e.g. USBLC6-2) at the connector, GND via right at its pin.

Mic bias

R4 feeds the mic from raw 5 V: add RC, e.g. 1 kΩ + 10 µF (f꜀ ≈ 16 Hz).

VIN

Header VIN connects to nothing: mark N/C or remove.

Observation

C1/C16/C17/C19 sit together, ~20 mm (measured on plot) from the VCC pins.

Why it matters

~1 nH/mm → ~20 nH. V = L·di/dt = 20 nH × 50 mA / 2 ns ≈ 0.5 V spike.

Fix

One 100 nF per VCC/GND pair, ≤3 mm, on the IC’s side; vias straight to GND.

Keep

C19 at AVCC (pin 100) and C18 at AREF (98), as close as possible.

USB D±

Route as a tight coupled pair (~90 Ω differential), no layer swaps, over unbroken GND.

ESD

Put the protector within a few mm of the connector, before anything else.

Crystal

HC-49 sits below the caps; use a 3.2 × 2.5 mm SMD part beside XTAL1/2.

Keep-out

No other signals under the crystal; GND under and around it.

Drop is the real limit

1 oz ≈ 0.5 mΩ/□. A 0.25 mm × 100 mm trace = 400 □ ≈ 0.2 Ω → 0.1 V lost at 0.5 A.

V3 rule

5 V from F1: ≥ 0.6–1.0 mm or a pour. Signals stay 0.2–0.25 mm.

Observation

Mic and its gain-of-100 preamp sit beside SD SPI traces and the button/RGB area.

Risk

Coupled clock edges are amplified 100× into ADC0.

Fix

Op-amp right at the mic; short input trace; GND pour around; SPI routed away.

Partition

Analog corner over unbroken GND — one plane, separated by placement, not cuts.

Silk

Overlapping refdes (C18/C19), text across pads and vias, long values printed (CD1206-S01575).

Assembly

SD socket pads are on the bottom layer — confirm side; two-sided assembly costs more.

Test

Only TP_VUCAP: add 5V, 3V3, GND test points and loops.

Fab

Add 3 fiducials if the board will be machine-assembled.