Tutorial 5: Op Amp Layout

In this tutorial, we will layout a simple version of an Op Amp. (this tutorial is much more brief than the previous tutorials, go back to find out the details if needed).
The LTSpice simulation file can be found here (You can check the NMOS and PMOS sizing information in the LTSpice version).

1. Copy your tutorial_4.jelib in the same folder, and rename it as tutorial_5.jelib.
2. Open this library in Electric, create a new schematic and layout cell called bias_circuit and Op_Amp respectively.

3. Make the schematic and icon view for the bias_circuit:

4. Make the layout view of the bias_circuit. Note that the PMOS and nWell should be covered in the region of a Pure N-Well-Node (Components - Pure - N-Well-Node).

The size of N-Well-Node can be re-sized using the 'special click' and click 'y'.

The same concept applied to the NMOS, the PWell and the P-Well-Node.

5. In the Op_Amp library, draw the schematic and icon: (Use the bias_circuit icon in your Op Amp circuit).

6. Create the layout of the Op Amp (drag the bias_circuit layout into your Op Amp layout). Make sure you have ZERO DRC/NCC/ERC errors. Copy the screenshot of the message window which has the DRC, NCC, and ERC clean messages for credit.

This is the end of the tutorial.