Figure 3: Sub cell layout.
Using the sub cell icon, the full ladder was layed out.
Figure 4: Layout of resistor ladder.
A DRC and NCC Check was run.
Figure 5: DRC check.
Figure 6: NCC check.
The schematic was then simulated using the ideal ADC.
Figure 7: Design simulation.
Discussion:
The layout and schematic of the DAC was
simplified into sub cells. These sub cells were used to form the larger
R-2R ladder that forms the DAC. DRC and NCC checks were performed to
ensure that the design was error free and consistent. The design was
then simulated to ensure that it functions correctly.