Lab 5
CE 351
James Ferguson


The goal of this lab is to create an inverter in Electric VLSI as well as simulate the schematic and layout.


The following shows the schematic and layout of a inverter.

DRC, ERC, and NCC all ran without any errors.

A larger inverter was also designed.

Again, DRC, ERC, and NCC all ran without any errors.


The following two figures show spice simulation results for the smaller inverter.

The two inverters where then sumulated together with a 10pF load in LT Spice.

A simalar simulation was run with the built in tool ALS.

The IRSIM simulatiom produced no results only logging that there where pending events.

The IRSIM doccumentation mentions that "This means that at the time that the simulation step ended, not all of the nodes in your simulation have settled" but does not mention how to resolve this issue.


The inversters worked as expected. The larger inverter was able to charget the capacitor quicker due to its size allowing more current to flow through.