338: Digital Electronics (Laboratory), Fall 2021
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Lab 1 Review of Superposition, Thevenin's Equivalent Circuit, and LTSpice. Due Monday 9/6 at 10 pm.
9/7, Lab 2 Design an R-2R DAC. Due Monday 9/13 at 10 pm.
9/14, Lab 3 Layout the R-2R DAC. Due Monday 9/20 at 10 pm.
9/21, Lab 4 MOSFETs and IV Curves. Due Monday 9/27 at 10 pm.
9/28, Lab 5 The Inverter. Due Monday 10/4 at 10 pm.
10/5 and 10/12, Lab 6 Build a NAND, NOR, XOR, and Full Adder. (2-week lab) Due Monday 10/18 at 10 pm
(I'll come to the lab at 8:30 am during the
morning session and leave at 1:30 pm during the afternoon session for
two ABET meetings with our external evaluators. Please prepare for not
having me before 8:30 am and after 1:30 pm)
10/19, Lab 7 Using Buses in ElectricVLSI. Due 10/25 at 10 pm.
10/26 and 11/2, Lab 8 Design a MUX, and a High-Speed Full Adder. Due 11/8 at 10 pm.
11/9 and 11/16, Lab 9 Design an 8-Bit ALU. Due 12/6 at 10 pm.
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