ENGR337 Lab 2020 Spring
Lab 7
Name: Kurt Emslie
Email: kdemslie@fortlewis.edu

1. Building an d Simulating NMOS & PMOS Transistors in ElectricVLSI for ID Curves

2. Introduction
In this lab we were tasked with designing NMOS and PMOS transistors in ElectricVLSI and running simulations on them for their respective ID curves.

3. Materials and Methods
ElectricVLSI was used to design the NMOS and PMOS circuits. LTSpice was iterfaced with the ElectricVSLI to run the simulations on the circuits. NMOS nad PMOS transistors were selected from the component list in their respective schematic drawing in ElectricVLSI. The transistors had to be changed from their default setting to a 4-terminal configuration. NMOS and PMOS transistors were then selected from the component lists in their respective layout drawings in ElectricVLSI. Both layouts erquired  two Acts. TwElectricVLSIo nActs for the NMOS transistor, and two pActs for the PMOS tranistors. These would be the sources and drains for the transistors. The NMOS transistor was connected to the lowest potential in the circuit, the ground. The PMOS was connected to the highest potential in the circuit. The gate of the PMOS was connected to a metal pad, becoming the terminal of the circuit. The PMOS also required a pwell to connect substrate to the highest potential in the circuit.
Each node on the layout had to labeled and exported to allow LTSpice to run simulations on the circuits. Numerous ERC well checks were ran to verify there were no errors in the circuit that would prevent the simulation from being ran. The LTSpice simulation was ran utilizing a the DC sweep function from 0-5V for the gate voltages.

4. Results

Figure 1: The Electric VLSI NMOS schematic.


Figure 2: The Electric VLSI NMOS layout.


Figure 3: The LTSpice simulation of the NMOS ID curve.


Figure 4: The LTSpice simulation of the NMOS-4 ID curve.


Figure 5: The Electric VLSI PMOS schematic.


Figure 6: The Electric VLSI PMOS layout.


Figure 7: The LTSpice simulation of the PMOS IS curve.
 

Figure 8: The LTSpice simulation of the PMOS-4 IS curve.

5. Discussion
The results form the simulation were as expected, after seeing the ID, and Is curves in previous work done in class. It is owrth mentioning that the manner in which LTSpice defines the direction of current flow can lead to a ID or IS curve being inverted due to polarity. What is important it to recognize the linear region and saturation regions of the curves. The linear regions are where the voltage is increasing. The saturation regions are where the current is leveling out a the peak values of the curves. The NMOS transistors increasesd VGS as the DC voltage is swept through the circuit. At low voltage there is no curent flow due to the threshhold voltage not being overcome. The same attributes were demonstrasted for the PMOS transistors.
This lab built upon the previous lab. This lab wil become the building block for the next lab, until all the layers are designed and build for the ultimate goal of being bale to design and build a semiconductor.