ENGR337 Lab 2020 Spring
Lab 7 MOSFETs and IV Curves
Name: Donovan Birky
Email: dkbirky@fortlewis.edu

1. Title - MOSFETs and IV Curves

2. Introduction
The goal for this lab was to continue to get familiar with chip design and simulation via Electric VLSI by creating a PMOS and NMOS transistor and simulating the associated IV curves.

3. Materials and Methods
ElectricVLSI software was required for this lab. First, the NMOS and PMOS transistors were placed into the schematic of ElectricVLSI. This required changing the default transistor to a 4-terminal PMOS and NMOS configuration. Next, the layout was created for each transistor type. The PMOS layout requires a pmos and two pActs (source and drain). The gate of the pmos is connected to a metal pad which will serve as the gate terminal on the chip. A pwell is also placed so that is connects to the subrate, which is connected to the highest potential in the circuit. The NMOS is connected similarly, but this time the nwell will be connected to the lowest potential (ground). The important part here was to ensure that the layout was as compact as possible, the proper SPICE model was labeled, and each node was exported to the proper name for simulation. An ENC check (well check) was conducted to ensure that none of the wells were misconnected. The simulation conducted for all of the configurations was a DC sweep of the drain voltage from 0 to 5 V for 5 different gate voltages.  Next, the corresponding schematics were created and also simulated. Again, the nodes had to be exported with the proper names and a NCC check was done to ensure that the nodes matched both the schematic and the layout. Simulations were run for the schematics as well.

4. Results

          Figure 1. NMOS schematic.


                                                             Figure 2. NMOS schematic simulation.


            Figure 3. NMOS layout.


                                                                  Figure 4. NMOS layout simulation.


           Figure 5. PMOS schematic.


                                                           Figure 6. PMOS schematic simulation.


                    Figure 7. PMOS layout.


                                                       Figure 8. PMOS layout simulation.

5. Discussion
The simulations matched expectations for all four of the various simulations run in this lab. For the NMOS, the currents were negative, but this is soley due to the fact of how LTSpice defines the directions of currents in transistors (it defines positive as going into the node), so even though these values were negative, they still match the expectation that eventually the current will saturate. Also, as VGS is increased for the NMOS, we can see that a higher and higher current is attained. Also, at very low voltage at VGS, no current flows because the NMOS isn't even powered up at this stage. The same goes for the PMOS, both simulations resulted in matched expectations with theory. Overall, the lab was successful in building the layouts for the NMOS and PMOS transistors, which can now be used to create more complicated layouts in the future.